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DSPIC30F5011T-20I/PT
Product Features
High-Performance dsPIC30F core
Modified Harvard architecture
C compiler optimized instruction set architecture
24-bit wide instructions, 16-bit wide data path
Up to 30 MIPS operation
DSP Engine for math intensive operations
Modulo and Bit-Reversed Addressing modes
Two, 40-bit wide accumulators with optional saturation logic
17-bit x 17-bit single cycle hardware fractional/ integer multiplier
Single cycle Multiply-Accumulate (MAC) operation
40-stage Barrel Shifter
Dual data fetch
Operating Conditions
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Peripheral Features
High current sink/source I/O pins: 25 mA/25 mA
Optionally pair up 16-bit timers into 32-bit timer modules
3-wire SPI™ modules (supports 4 Frame modes)
I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
Addressable UART modules with FIFO buffers and selectable pins
Data Converter Interface (DCI) supports common audio Codec protocols, including I2S and AC’97
Two CAN bus modules compliant with CAN 2.0B standard
Analog Features
12-bit 200 Ksps Analog-to-Digital Converter (A/D)
A/D Conversion available during Sleep and Idle
1 Sample/Hold
Multiple Conversion Sequencing Options
Special Microcontroller Features
Enhanced Flash program memory with 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)
Data EEPROM memory with 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)
Self-reprogrammable under software control
Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator for reliable operation
Fail-Safe clock monitor operation
Detects clock failure and switches to on-chip low power RC oscillator
Programmable code protection
In-Circuit Serial Programming™ (ICSP™)
DC to 40 MHz external clock input
Internal FRC input with PLL active (4x, 8x, 16x)
4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
Programmable Brown-out Detection and Reset generation
Sleep, Idle and Alternate Clock modes for power management
Parametrics
CPU Type | dsPIC® DSC |
CPU Speed (MHz) | 30 |
Program Memory Size (KB) | 66 |
Multiple Flash Panels | No |
Temp. Range Min.(C°) | -40 |
Temp. Range Max.(C°) | 125 |
Operation Voltage Min.(V) | 2.5 |
Operation Voltage Max.(V) | 5.5 |
Pin Count | 64 |
Low Power | No |
Number of Comparators | 0 |
Number of ADCs | 1 |
ADC Channels | 16 |
Max ADC Resolution (bits) | 12 |
Max ADC Sampling Rate (ksps) | 200 |
Number of DACs | 0 |
DAC outputs | 0 |
Max DAC Resolution (bits) | 0 |
Hardware RTCC | No |
Motor Control PWM Channels | 0 |
SMPS PWM Channels | 0 |
Number of PWM Time Bases | 1 |
Output Compare Channels | 8 |
Number of CAN Modules | 2 |
Type of CAN module | CAN |
Crypto Engine | No |
Quadrature Encoder Interface (QEI) | 0 |
Segment LCD | 0 |
LCD/Graphics Interface | No |
Configurable Logic Cell Modules (CLC /CCL) | 0 |
Peripheral Pin Select (PPS)/Pin Muxing | No |