DSPIC30F5016-30I/PT

Peripheral Features

• High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • 16-bit Capture input functions • 16-bit Compare/PWM output functions • 3-wire SPI modules (supports four Frame modes) • I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing • UART module with FIFO Buffers • CAN module, 2.0B compliant

High-Performance Modified RISC CPU

• Modified Harvard architecture • C compiler optimized instruction set architecture with flexible Addressing modes • 83 base instructions • 24-bit wide instructions, 16-bit wide data path • 66 Kbytes on-chip Flash program space (Instruction words) • 2 Kbytes of on-chip data RAM • 1 Kbyte of nonvolatile data EEPROM • Up to 30 MIPS operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x) • 36 interrupt sources: - Five external interrupt sources - Eight user-selectable priority levels for each interrupt source - Four processor trap sources • 16 x 16-bit working register array

Motor Control PWM Module Features

• Eight PWM output channels - Complementary or Independent Output modes - Edge and Center-Aligned modes • Four duty cycle generators • Dedicated time base • Programmable output polarity • Dead-Time control for Complementary mode • Manual output control • Trigger for A/D conversions

DSP Engine Features

• Dual data fetch • Accumulator write back for DSP operations • Modulo and Bit-Reversed Addressing modes • Two 40-bit wide accumulators with optional saturation logic • 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier • All DSP instructions single cycle • ±16-bit single-cycle shift

DSPIC30F5016-30I/PT

Peripheral Features

• High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • 16-bit Capture input functions • 16-bit Compare/PWM output functions • 3-wire SPI modules (supports four Frame modes) • I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing • UART module with FIFO Buffers • CAN module, 2.0B compliant

High-Performance Modified RISC CPU

• Modified Harvard architecture • C compiler optimized instruction set architecture with flexible Addressing modes • 83 base instructions • 24-bit wide instructions, 16-bit wide data path • 66 Kbytes on-chip Flash program space (Instruction words) • 2 Kbytes of on-chip data RAM • 1 Kbyte of nonvolatile data EEPROM • Up to 30 MIPS operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x) • 36 interrupt sources: - Five external interrupt sources - Eight user-selectable priority levels for each interrupt source - Four processor trap sources • 16 x 16-bit working register array

Motor Control PWM Module Features

• Eight PWM output channels - Complementary or Independent Output modes - Edge and Center-Aligned modes • Four duty cycle generators • Dedicated time base • Programmable output polarity • Dead-Time control for Complementary mode • Manual output control • Trigger for A/D conversions

DSP Engine Features

• Dual data fetch • Accumulator write back for DSP operations • Modulo and Bit-Reversed Addressing modes • Two 40-bit wide accumulators with optional saturation logic • 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier • All DSP instructions single cycle • ±16-bit single-cycle shift