IS42S16160J-7TLI

Description

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture.  All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.

DEVICE OVERVIEW

The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256Mb SDRAM includes an AUTOREFRESH MODE, and a power-saving, power-down mode. All signals are  registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address  generation, the ability to interleave between internal banks  to hide precharge time and the capability to randomly  change column addresses on each clock cycle during  burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTOPRECHARGE function enabled. Precharge one bank while accessing one of the  other three banks will hide the precharge cycles and provide  seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting  at a selected location and continuing for a programmed  number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are  used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location  for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.

FUNCTIONAL BLOCK DIAGRAM (For 4Mx16x4 Banks SHOWN)

OPTIONS 

•  Package: 54-pin TSOP-II 54-ball BGA 

•  Operating Temperature Range:

Commercial (0o C to +70o C) 

Industrial (-40o C to +85o C) 

Automotive Grade A1 (-40o C to +85o C) 

Automotive Grade A2 (-40o C to +105o C)

IS42S16160J-7TLI

Description

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture.  All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows.

DEVICE OVERVIEW

The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256Mb SDRAM includes an AUTOREFRESH MODE, and a power-saving, power-down mode. All signals are  registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address  generation, the ability to interleave between internal banks  to hide precharge time and the capability to randomly  change column addresses on each clock cycle during  burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTOPRECHARGE function enabled. Precharge one bank while accessing one of the  other three banks will hide the precharge cycles and provide  seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting  at a selected location and continuing for a programmed  number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are  used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location  for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.

FUNCTIONAL BLOCK DIAGRAM (For 4Mx16x4 Banks SHOWN)

OPTIONS 

•  Package: 54-pin TSOP-II 54-ball BGA 

•  Operating Temperature Range:

Commercial (0o C to +70o C) 

Industrial (-40o C to +85o C) 

Automotive Grade A1 (-40o C to +85o C) 

Automotive Grade A2 (-40o C to +105o C)