W631GG6NB-11 

GENERAL DESCRIPTION 

The W631GU6NB is a 1G bits DDR3L SDRAM, organized as 8,388,608 words  8 banks  16 bits. This  device achieves high speed transfer rates up to 2133 MT/s (DDR3L-2133) for various applications. This  device is sorted into the following speed grades: -09, -11, -12, -15, 09I, 11I, 12I, 15I, 09J, 11J, 12J and  15J. The -09 ,09I and 09J speed grades are compliant to the DDR3-2133L (14-14-14) specification (The 09I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 09J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -11 ,11I and 11J speed grades are compliant to the DDR3L-1866 (13-13-13) specification (The 11I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 11J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -12, 12I and 12J speed grades are compliant to the DDR3L-1600 (11-11-11) specification (The 12I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 12J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -15, 15I and 15J speed grades are compliant to the DDR3L-1333 (9-9-9) specification (The 15I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 15J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The W631GU6NB is designed to comply with the following key DDR3L SDRAM features such as  posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and  asynchronous reset. All of the control and address inputs are synchronized with a pair of externally  supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous  fashion.

2. FEATURES 

⚫ Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V ⚫ Backward compatible to VDD, VDDQ = 1.5V ± 0.075V ⚫ Double Data Rate architecture: two data transfers per clock cycle ⚫ Eight internal banks for concurrent operation ⚫ 8 bit prefetch architecture ⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 ⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) ⚫ Programmable read burst ordering: interleaved or nibble sequential ⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data ⚫ Edge-aligned with read data and center-aligned with write data ⚫ DLL aligns DQ and DQS transitions with clock ⚫ Differential clock inputs (CK and CK#) ⚫ Commands entered on each positive CK edge, data and data mask are referenced to both edges of  a differential data strobe pair (double data rate) ⚫ Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,  address and data bus efficiency ⚫ Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) ⚫ Auto-precharge operation for read and write bursts ⚫ Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) ⚫ Precharged Power Down and Active Power Down ⚫ Data masks (DM) for write data ⚫ Programmable CAS Write Latency (CWL) per operating frequency ⚫ Write Latency WL = AL + CWL ⚫ Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence ⚫ System level timing calibration support via write leveling and MPR read pattern ⚫ ZQ Calibration for output driver and ODT using external reference resistor to ground ⚫ Asynchronous RESET# pin for Power-up initialization sequence and reset function ⚫ Programmable on-die termination (ODT) for data, data mask and differential strobe pairs ⚫ Dynamic ODT mode for improved signal integrity and preselectable termination impedances during  writes ⚫ 2K Byte page size ⚫ Packaged in VFBGA 96 Ball (7.5 x13 mm2 with thickness of 1.0 mm) - (Window BGA Type), using lead free materials with RoHS compliant

W631GG6NB-11 

GENERAL DESCRIPTION 

The W631GU6NB is a 1G bits DDR3L SDRAM, organized as 8,388,608 words  8 banks  16 bits. This  device achieves high speed transfer rates up to 2133 MT/s (DDR3L-2133) for various applications. This  device is sorted into the following speed grades: -09, -11, -12, -15, 09I, 11I, 12I, 15I, 09J, 11J, 12J and  15J. The -09 ,09I and 09J speed grades are compliant to the DDR3-2133L (14-14-14) specification (The 09I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 09J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -11 ,11I and 11J speed grades are compliant to the DDR3L-1866 (13-13-13) specification (The 11I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 11J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -12, 12I and 12J speed grades are compliant to the DDR3L-1600 (11-11-11) specification (The 12I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 12J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The -15, 15I and 15J speed grades are compliant to the DDR3L-1333 (9-9-9) specification (The 15I  industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C, the 15J industrial plus grade which is guaranteed to support -40°C ≤ TCASE ≤ 105°C). The W631GU6NB is designed to comply with the following key DDR3L SDRAM features such as  posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and  asynchronous reset. All of the control and address inputs are synchronized with a pair of externally  supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous  fashion.

2. FEATURES 

⚫ Power Supply: 1.35V (typ.), VDD, VDDQ = 1.283V to 1.45V ⚫ Backward compatible to VDD, VDDQ = 1.5V ± 0.075V ⚫ Double Data Rate architecture: two data transfers per clock cycle ⚫ Eight internal banks for concurrent operation ⚫ 8 bit prefetch architecture ⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14 ⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF) ⚫ Programmable read burst ordering: interleaved or nibble sequential ⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data ⚫ Edge-aligned with read data and center-aligned with write data ⚫ DLL aligns DQ and DQS transitions with clock ⚫ Differential clock inputs (CK and CK#) ⚫ Commands entered on each positive CK edge, data and data mask are referenced to both edges of  a differential data strobe pair (double data rate) ⚫ Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,  address and data bus efficiency ⚫ Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) ⚫ Auto-precharge operation for read and write bursts ⚫ Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) ⚫ Precharged Power Down and Active Power Down ⚫ Data masks (DM) for write data ⚫ Programmable CAS Write Latency (CWL) per operating frequency ⚫ Write Latency WL = AL + CWL ⚫ Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence ⚫ System level timing calibration support via write leveling and MPR read pattern ⚫ ZQ Calibration for output driver and ODT using external reference resistor to ground ⚫ Asynchronous RESET# pin for Power-up initialization sequence and reset function ⚫ Programmable on-die termination (ODT) for data, data mask and differential strobe pairs ⚫ Dynamic ODT mode for improved signal integrity and preselectable termination impedances during  writes ⚫ 2K Byte page size ⚫ Packaged in VFBGA 96 Ball (7.5 x13 mm2 with thickness of 1.0 mm) - (Window BGA Type), using lead free materials with RoHS compliant