[Baoxingwei] USB interface （1）

Common identification and standards and functions

The pin definition

ID pin is only used in OTG function. Mini-USB ports include Mini-A, B, and AB ports.

If your system is used only as a Slave, then use the B interface.

The system controller will judge the level of ID pin to determine what kind of device is inserted. If the level is high, the B connector is inserted, and then the system will be in master mode.

If the ID is low, interface A is inserted, and the system uses the HNP protocol to determine which will be the Master and which will be the Slave.

These instructions are for technical staff summary, for reference only.

What we usually use on our phones is a type B Mini-USB port, a USB cable with a Mini-USB port.

Internal structure

USB interface circuit uses DIUSBD12 chip, which is a kind of USB device with high cost and performance. It is usually used to communicate with ARM universal interface and support local DMA transmission. The device adopts a modular approach to implement a USB interface, allowing the use of existing architecture and minimizing firmware investment. This flexibility reduces development time, risk, and cost by using existing architectures and reducing investment in firmware, and is an effective way to develop low-cost and efficient USB peripheral solutions.

SIE, the built-in serial interface engine of PDIUSBD12, implements all the USB protocol layer and is completely realized by hardware without the involvement of firmware. The functions of this module include: synchronous pattern recognition, parallel/serial conversion, bit fill/unfill, CRC check/generation, PID check/generation, address recognition and handshake evaluation/generation.

The internal structure of PDIUSBD12 is shown

Figure PDIUSBD12 internal structure block diagram

Among them:

· Analog transceiver: Integrated transceiver interface can be directly connected to USB via terminal resistance.

· Voltage regulator: A 3.3V regulator is integrated into the chip for the power supply of the analog transceiver.

·PLL: Integrated 6MHZ to 48MHZ clock multiplication on chip, allowing the use of low cost 6MHZ crystal oscillator, electromagnetic interference is also reduced due to the use of low frequency crystal oscillator.

· Bit clock recovery: The bit clock recovery circuit adopts the 4x oversampling principle to recover the clock from the input USB data stream and can track the jitter and frequency drift within the specified range of USB.

·Soft-Connect: High-speed devices connect to USB by D+ through a 1.5 kΩ pull-up resistor. The 1.5kQ pull-up resistor is integrated in the USB chip and is not connected to Voc by default. The connection is established by sending a command from ARM, which allows ARM to complete the initialization sequence before deciding to establish a connection with USB.

The USB bus connection can be reinitialized without unplugging the cable.

· Good-link: Provides Good USB connection indication. In enumeration, the LED indicator flashes intermittently according to the status of communication. When the USB is successfully enumerated and configured, the LED indicator will remain on. During USB data transmission, the LED will flash; During the suspension, the LED goes out. This feature provides a user-friendly indication of USB devices, hubs, and USB communication status. As a diagnostic tool, it is useful for isolating malfunctioning devices, reducing the cost of on-site support and hotlines.

· Storage space Management Unit (MMUs) and Integrated RAM: The MMUs and integrated RAM act as buffers for speed differences between USB when transferring at 12Mb/s and connecting to ARM. This allows ARM to read and write USB packets at its own speed.

· Parallel and DMA interface: To ARM processors, the PDIUSBD12 looks like a memory device with an 8-bit data bus and an address bit (occupying 2 locations). It supports independent and time-multiplexed address and data buses, as well as DMA transfers that read directly between the primary endpoint and local shared RAM, as well as single-cycle and burst-mode DMA transfers.